1. Field of the Invention
Generally, the present disclosure relates to the field of manufacturing of integrated circuits and semiconductor devices, and, more particularly, to an integrated circuit product with die-die stacking structures comprising connectors between individual dies and methods of making such structures.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. Miniaturization and increase of circuit densities represent ongoing demands.
A conventional die (chip) is usually mounted on some form of substrate, such as a package substrate or a printed circuit board. Electrical connectivity between the die and the underlying substrate or board is established through a variety of conventional mechanisms. In one example, a so-called flip-chip configuration, the active circuitry side of the die is provided with a plurality of electrically conductive balls or bumps that are designed to establish a metallurgical bond with a corresponding plurality of conductor pads positioned on the substrate or circuit board. The die is flipped over and seated with the active circuitry side facing downwards on the underlying substrate.
Recently, stacked die configurations have been developed in order to increase performance and high-density integration of semiconductor devices. Electrical interconnects must be established between the stacked dies. Several conventional techniques for stacking dies have been considered. In one conventional variant, a relatively small semiconductor die is positioned on the bulk semiconductor side of a much larger semiconductor die. Bonding wires are used to establish the electrical conductivity between the upper die and the lower die. The difficulty associated with this approach is that the bonding wires represent relatively long electrical pathways and thus exhibit higher than desired inductance and proportionally slower electrical performance. In addition, the bulk semiconductor side is not available for heat sink mounting.
A so-called multi-chip module (MCM) package is commonly used in the assembly package and electronic devices. Usually, the MCM package mainly comprises at least two chips encapsulated therein so as to upgrade the electrical performance of the package. A first chip carrier is joined “back to back” with a second chip carrier via an insulating adhesive applied on the inactive surface of the first chip mounted on the first chip carrier and the inactive surface of the second chip mounted on the second chip carrier. The two inactive surfaces are bonded together to form a multi-chip module. Both the topmost or upper-most surface and the lower-most surface of the multi-chip module are capable of being electrically connected with other components, thereby eliminating one of the obstacles associated with vertically stacking chips in flip-chip technology and further varying arrangement flexibility of the chips in a package.
In particular, stacked dies may be electrically connected to each other by means of through-silicon vias (TSVs) as illustrated in FIG. 1. FIG. 1 shows a die 10 embedded in a substrate 11. The die 10 comprises two TSVs 12 and 13. The die 10 comprises an active region 14 comprising an integrated circuit. Die bond pads 15 are connected to the active region 14 of the die 10 and to conductors 16. The conductors 16 are connected to bump bond pads 17 in a lower layer of the substrate 11 to which conductive bumps 18 are adhered. In the depicted prior art example, six additional dies 20, 30, 40, 50, 60 and 70 are stacked vertically above the lower most die 10 and each of the additional dies 20, 30, 40, 50, 60 and 70 comprises TSVs and active portions. Electrical connections between the individual dies 10 to 70 are provided by conductive bumps 19. However, as shown in FIG. 1, this design also requires a plurality of external conductors 16 and thus exhibits relatively long electrical pathways for signal transfer.
As already mentioned, in the art, a large variety of die stacking techniques, including a variety of electrical die-die connections, are proposed as, for example, a stack of a relatively small semiconductor die positioned on the bulk semiconductor side of a much larger semiconductor die wherein bonding wires are used to establish the electrical conductivity between the upper die and the lower die. The bonding wires exhibit long electrical pathways and thus a relatively high inductance and low electrical performance. According to another approach, electrical interconnects between upper and lower dies are provided by a plurality of conductor traces that are formed on the bulk silicon side of the lower die. Again, the conductor traces represent relatively high inductance pathways and thus limit speed performance. Furthermore, the bulk silicon side is not available for a heat sink in this approach.
In view of the situation described above, the present disclosure provides techniques of die-die stacking with improved signal transfer from die to die, in particular, with respect to enhanced signaling speed and standardization ability, as compared to the art.